The rapid development of artificial intelligence (AI) and high-performance computing (HPC) has led to an explosive growth in demand for high-computing-power chips. AI training and inference, data centers and supercomputing systems set unprecedented requirements for computing density, memory bandwidth and energy efficiency. Meanwhile, Moore's Law, which traditionally relies on transistor miniaturization, is gradually slowing down. Simply boosting performance by advancing manufacturing processes has encountered bottlenecks in cost, power consumption and production yield.

Against this backdrop, 2.5D and 3D advanced packaging technologies have become vital approaches to improving system-level performance. Through chiplet and heterogeneous integration, advanced packaging realizes high-density interconnections between logic chips, high-bandwidth memory (HBM), I/O devices, analog/RF components and other units manufactured via different processes at the packaging stage. This significantly increases system bandwidth, reduces interconnection power consumption and shortens signal transmission paths.

Nevertheless, conventional organic substrates can no longer meet the demand for ultra-high I/O density due to limitations in routing precision, signal integrity and power integrity. Silicon interposers, by contrast, are plagued by high manufacturing costs, size constraints, complicated thermal management, as well as difficulties in stress control and yield optimization.

With distinctive material and performance merits, glass substrates have become an ideal alternative to organic carriers and silicon interposers. In terms of material properties, glass substrates feature ultra-low surface roughness, excellent dimensional stability and tunable coefficient of thermal expansion (CTE). They effectively alleviate thermal mismatch between chips and substrates, lowering the risks of packaging warpage and interconnection failure. In terms of functional performance, their low dielectric constant and low-loss characteristics reduce signal transmission delay and crosstalk, and greatly enhance high-speed signal integrity. Thanks to the above advantages, glass substrates are well suited for large-scale heterogeneous integration. They support large-area layout and high-I/O-density interconnections, fully complying with the application requirements of AI and HPC chips.

Electroplating serves as an optimal metallization technology for electrical interconnection of glass substrates, as it enables high-quality metal filling at low cost. The metallization procedures mainly include through-glass via (TGV) metallization, redistribution layer (RDL) metallization on glass substrates, and micro-bump metallization for interconnection with logic chips.

For the TGV process, vias are first formed on glass by laser-induced etching and other methods. Afterwards, solid metal filling is completed by electroplating on the sputtered seed layer. The main technical challenges include poor adhesion between metal and glass, defect-free filling of high-aspect-ratio structures, and glass cracking in subsequent processes.

In the RDL process, a seed layer is deposited on the glass substrate by sputtering first. Photolithography is then adopted to form routing patterns, followed by electroplating to accomplish RDL metallization. Its major difficulties lie in void defect control and pattern integrity maintenance.

The micro-bump process shares basically the same workflow as the RDL process. The difference lies in that micro-bumps are stacked structures composed of copper, nickel, tin-silver alloy and gold. The key technical difficulties are controlling void defects in each metal layer and ensuring the overall integrity of micro-bumps.

Auxiliary Pre-Treatment Processes for Electroplating

Apart from core electroplating processes and interconnection reliability control, glass-based advanced packaging involves a series of auxiliary procedures that directly affect electroplating quality. Distributed before and after electroplating, these processes are closely associated with wetting performance, surface state regulation and residual stress relief, thus requiring dedicated discussion.

Wetting treatment for high-aspect-ratio structures and plasma treatment are two major pre-electroplating processes. The former improves the infiltration capacity of electroplating solution into microstructures, while the latter modulates the surface condition of seed layers. For high-aspect-ratio structures such as TGVs, the large contact angle between electroplating solution and via walls prevents the solution from fully penetrating the vias spontaneously. Therefore, wetting treatment is indispensable to guarantee uniform and complete electroplating.

Patterns for micro-bumps and RDLs are fabricated through photolithography, exposure and development. Organic residues from previous procedures and the poor wettability of dielectric materials such as polyimide (PI) will hinder the electroplating solution from reaching the seed layer and destabilize interfacial reactions. For this reason, plasma treatment is commonly applied prior to electroplating.

Plasma Treatment

Plasma treatment adopts low-pressure ionized gas as the working medium. It removes surface contaminants, regulates oxide layers and activates material surfaces via ion bombardment and free radical reactions, acting as a critical pre-treatment process before electroplating.

Plasma pre-treatment for RDL and copper micro-bumps has identical core purposes, namely removing photoresist residues, restraining oxidation of seed layers, and optimizing the interfacial bonding of subsequent electroplated layers. Different process gases are selected according to actual treatment demands.

Nitrogen (N₂) plasma has relatively limited cleaning effect and is mainly used to remove minor surface residues. Oxygen (O₂) plasma is widely applied when heavy photoresist residues exist or higher surface activity is needed. Relevant studies have verified that O₂ plasma treatment generates polar groups including C=O and O=C—OH on material surfaces, which improves surface hydrophilicity. The corresponding effect is shown in Figure 1.

Figure 1 Contact angle of PI film after O₂ plasma treatment  

The combined use of O₂ and argon (Ar) plasma before copper electroplating can further strengthen the bonding performance between electroplated copper and copper seed layers and reduce interfacial voids. This combined treatment effectively eliminates copper oxide on the seed layer surface and lowers the occurrence probability of interfacial defects.

In addition, treatment with pure Ar plasma can properly increase the surface roughness of copper seed layers, so as to enhance the mechanical interlocking between electroplated layers and seed layers.

Beyond the pre-treatment for copper electroplating, plasma treatment before tin-silver (SnAg) electroplating for C2-style micro-bumps can effectively eliminate impurities and mitigate defects in intermetallic compound (IMC) layers.