Advanced packaging has emerged as a core technological path in the post-Moore's Law era. It imposes atomic-level requirements on interfacial cleanliness, wettability and patterning precision, creating an urgent need for innovation in conventional processes. As packaging technologies evolve, chips and interconnect structures become increasingly miniaturized and complex, and process reliability issues grow more prominent. Multiple rounds of cleaning and activation are often required from chip fabrication to packaging to achieve high-performance packaging. Oxidation of lead frames in wire bonding (WB) tends to cause failures at the bonding interface of lead pins and pads. In the multi-layer RDL lithography and etching process on interposers for 2.5D/3D packaging, residual photoresist on via sidewalls raises void rates during Cu filling. Remaining photoresist in RDL traces further compromises the integrity of Cu routing patterns and reduces interconnect reliability. Meanwhile, organic contaminants near micro bumps between interposers and chips impair the wetting performance of underfill, resulting in voids between underfill and bumps. This exacerbates coefficient of thermal expansion (CTE) mismatch and triggers failures at solder joints and the interface between underfill and chips. Effective cleaning and activation of chips prior to molding also improves the interfacial reliability between epoxy molding compound (EMC) and chips, and mitigates failures induced by moisture ingress. Conventional wet cleaning and activation using chemical solvents alone struggle to meet structural precision requirements in packaging processes. When penetrating deep trenches, cleaning solvents can only be removed via evaporation, which leaves contaminants behind. As a key dry cleaning technology, plasma cleaning and activation is now widely adopted in IC manufacturing and delivers excellent results in enhancing surface cleanliness.

Plasma Cleaning Processes for Chip Packaging

Plasma processing technology is extensively applied in semiconductor chip packaging fabrication. Multiple plasma processing steps are typically deployed before and after chip packaging. Common plasma processes include deposition, etching, photoresist stripping, as well as cleaning, activation and modification. Among these, plasma cleaning involves the most complex and elaborate workflows. Typical plasma cleaning processes are summarized below:

1. Bulk photoresist removal: Strip bulk photoresist after plasma etching or ion implantation.

2. Residue removal: Eliminate residues formed at the bottom and sidewalls of etched vias or trenches from ablation of underlying stop layers, etch stop layers or metal layers. It also removes polymeric or inorganic residues generated to achieve selectivity to underlying materials and form anisotropic profile structures.

3. Pre-deposition cleaning: Prior to dielectric or metal thin-film deposition, remove organic residues, particulate contaminants and oxide layers on film surfaces to ensure favorable adhesion between deposited layers and substrates or form interfaces with low contact resistance, such as in TSV Cu pillar deposition and RDL routing deposition.

4. Surface modification: Modify or tune surfaces through chemical or physical means to suppress surface oxidation during process sequences, alter the chemical composition of surface films or impurity adsorption characteristics, and adjust surface tension. This promotes uniformity and process stability of subsequent wet processes (e.g. photoresist coating) or dry processes (e.g. plasma etching), and improves reliability of various interconnect interfaces within packages, such as EMC molding, underfill dispensing and wire bonding (WB).

Figure 1-1 illustrates the steps requiring plasma cleaning and activation in Fan-Out Wafer-Level Packaging (FOWLP) and Fan-Out Panel-Level Packaging (FOPLP). As a critical method to boost package reliability, plasma processing covers most process nodes.

Figure 1-1 Plasma Processing Steps in FOWLP and FOPLP

During RDL lithographic patterning, plasma photoresist stripping is performed to provide intact patterned traces for subsequent seed layer deposition and Cu routing electroplating. Plasma cleaning before Cu electroplating improves the quality and adhesion of electroplated layers. Prior to die attach, plasma cleaning ensures pre-bonding surfaces meet required cleanliness and enhances bonding quality. After die attach, plasma cleaning is also applied in pre-molding steps to activate surfaces and improve the adhesion and flowability of EMC around bonded chips. In addition, extra plasma cleaning is commonly carried out after molding to remove residues left after sacrificial layer removal. Post bumping, plasma cleaning eliminates residual flux and activates surfaces to improve the wettability of subsequent underfill across various interfaces.